Thin film transistors and methods of forming thin film transistors

ABSTRACT

A method of forming a thin film transistor over a substrate is provided whereby at least one of the source region or the drain region is conductively doped while preventing conductivity doping of the channel region without any masking of the channel region occurring by any separate masking layer. A method includes, a) providing a substrate having a node to which electrical connection is to be made; b) providing a first electrically insulative dielectric layer over the substrate; c) providing an electrically conductive gate layer over the first dielectric layer; d) providing a second electrically insulative dielectric layer over the electrically conductive gate layer; e) providing a contact opening through the second dielectric layer, the electrically conductive gate layer and the first dielectric layer; the contact opening defining projecting sidewalls; f) providing a gate dielectric layer within the contact opening laterally inward of the projecting sidewalls; g) providing a layer of semiconductive material over the second dielectric layer and within the contact opening against the gate dielectric layer and in electrical communication with the node; the semiconductive material within the contact opening defining an elongated and outwardly extending channel region the electrical conductance of which can be modulated by means of the adjacent electrically conductive gate and gate dielectric layers; and h) conductively doping the semiconductive material layer lying outwardly of the contact opening to form one of a source region or a drain region of a thin film transistor. Thin film transistor constructions are also disclosed.

PATENT RIGHTS STATEMENT

This invention was made with Government support under Contract No.MDA972-92-C-0054 awarded by Advanced Research Projects Agency (ARPA).The Government has certain rights in this invention.

TECHNICAL FIELD

This invention relates specifically to thin film transistor technology.

BACKGROUND OF THE INVENTION

As circuit density continues to increase, there is a corresponding driveto produce smaller and smaller field effect transistors. Field effecttransistors have typically been formed by providing active areas withina bulk substrate material or within a complementary conductivity typewell formed within a bulk substrate. One additional technique findinggreater application in achieving reduced transistor size is to formfield effect transistors with thin films, which is commonly referred toas “thin film transistor” (TFT) technology. These transistors are formedusing thin layers which constitute all or a part of the resultant sourceand drain regions, as opposed to providing both regions within a bulksemiconductor substrate.

Specifically, typical prior art TFT's are formed from a thin film ofsemiconductive material (typically polysilicon). A central channelregion of the thin film is masked by a separate layer, while opposingadjacent source/drain regions are doped with an appropriate p or n typeconductivity enhancing impurity. A gate insulator and gate are providedeither above or below the thin film channel region, thus providing afield effect transistor having active and channel regions formed withina thin film as opposed to a bulk substrate.

It would be desirable to improve upon methods of forming thin filmtransistors and in improving thin film transistor constructions.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is a diagrammatic sectional view of a semiconductor waferfragment at one processing step in accordance with the invention.

FIG. 2 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 1.

FIG. 3 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 2.

FIG. 4 is one example of a possible top view of FIG. 3.

FIG. 5 is a view of the FIG. 1 wafer fragment at a processing stepsubsequent to that shown by FIG. 3.

FIG. 6 is a diagrammatic sectional view of an alternate embodiment waferfragment in accordance with the invention.

FIG. 7 is a diagrammatic sectional view of yet another alternateembodiment wafer fragment at one processing step in accordance with theinvention.

FIG. 8 is a view of the FIG. 7 wafer fragment at a processing stepsubsequent to that shown by FIG. 7.

FIG. 9 is a view of the FIG. 7 wafer fragment at a processing stepsubsequent to that shown by FIG. 8.

FIG. 10 is a view of the FIG. 7 wafer fragment at a processing stepsubsequent to that shown by FIG. 9.

FIG. 11 is a view of the FIG. 7 wafer fragment at a processing stepsubsequent to that shown by FIG. 10.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section-8).

In accordance with one aspect of the invention, a method of forming athin film transistor over a substrate comprises the following steps:

providing a layer of semiconductive material from which a channel regionand at least one of a source region or a drain region of a thin filmtransistor are to be formed; and

conductively doping the at least one of the source region or the drainregion of the semiconductive material layer while preventingconductivity doping of the channel region of the semiconductive materiallayer, such doping being conducted without any masking of the channelregion by any separate masking layer.

In accordance with another aspect of the invention, a method of forminga thin film transistor comprises the following steps:

providing a substrate having a node to which electrical connection is tobe made;

providing a first electrically insulative dielectric layer over thesubstrate;

providing an electrically conductive gate layer over the firstdielectric layer;

providing a second electrically insulative dielectric layer over theelectrically conductive gate layer;

providing a contact opening through the second dielectric layer, theelectrically conductive gate layer and the first dielectric layer; thecontact opening defining projecting sidewalls;

providing a gate dielectric layer within the contact opening laterallyinward of the contact opening sidewalls;

providing a layer of semiconductive material over the second dielectriclayer and within the contact opening against the gate dielectric layerand in electrical communication with the node; the semiconductivematerial within the contact opening defining an elongated and outwardlyextending channel region the electrical conductance of which can bemodulated by means of the adjacent electrically conductive gate and gatedielectric layers; and

conductively doping the semiconductive material layer lying outwardly ofthe contact opening to form one of a source region or a drain region ofa thin film transistor.

In accordance with still another aspect of the invention, a thin filmtransistor comprises:

a thin film transistor layer having a source region, a channel regionand a drain region; the thin film channel region comprising an annulus;and

a gate in proximity to the thin film channel annulus, the gatecomprising an annulus which surrounds the thin film channel annulus.

These and other aspects of the invention will be more readilyappreciated from the following description with proceeds with referenceto the accompanying drawings.

Referring to FIG. 1, a semiconductor wafer fragment in process isindicated generally with reference numeral 10. Such comprises a bulksubstrate 12 of lightly doped p or n type monocrystalline silicon,having a diffusion region 13 provided therein. A first electricallyinsulative dielectric layer 14 (typical SiO₂) is provided over bulksubstrate 12. An example and preferred thickness range for layer 12 isfrom 50 Angstroms to 2000 Angstroms, with 100 Angstroms being morepreferred. An electrically conductive layer 16 is provided over firstdielectric layer 14. Layer 16 will ultimately comprise the conductivegate of the thin film transistor, and preferably comprises a heavilydoped (greater than 1×10²⁰ ion/cm³) layer of polysilicon. An example andpreferred thickness range is from 3000 Angstroms to 10,000 Angstroms,with 8000 Angstroms being more preferred. A second electricallyinsulative dielectric layer 18 is provided over electrically conductivegate layer 16. Such can be considered as a base layer over which a thinfilm transistor layer will be provided. An example and preferredmaterial is SiO₂ deposited to a thickness range of from 300 Angstroms to3000 Angstroms, with 1000 Angstroms being more preferred.

Referring to FIG. 2, a contact opening 20 is provided through seconddielectric layer 18, electrically conductive gate layer 16, and firstdielectric layer 14 to outwardly expose diffusion region 13.Alternately, diffusion region 13 could be provided after forming contactopening 20. One method of doing this is by using ion implantationthrough contact opening 20, thereby making diffusion regions 13self-aligned to contact opening 20. Contact opening 20 definesprojecting sidewalls 22 which in the preferred embodiment are providedto be substantially perpendicular relative to the expanse of bulksubstrate 12. A dielectric layer 24, which will serve as gate dielectriclayer, is deposited over second dielectric layer 18 and within contactopening 20 to a thickness which less than completely fills contactopening 20. An example diameter for contact opening 20 is 3500Angstroms, with an example layer 24 being SiO₂ deposited to a thicknessof 200 Angstroms in such instance.

Referring to FIG. 3, gate dielectric layer 24 is anisotropically etchedto define a resultant gate dielectric layer 26 within contact opening 20laterally inward of sidewalls 22. When anisotropically etching gatedielectric layer 24, some of second dielectric layer 18 is removedduring a desired overetch. If layer 18 is 1000 Angstroms thick and layer24 is 200 Angstroms thick, a preferred over-etch would be 200 Angstroms,reducing 18 to 800 Angstroms. In the illustrated and preferredembodiment, such gate dielectric layer takes on the shape or appearanceof conventional insulative sidewall spacers, and in the depictedembodiment is in the form or shape of a longitudinally elongatedannulus. Thus, electrically conductive gate layer 16 also is comprisedof an annulus which surrounds contact opening 20.

FIG. 4 illustrates one example of a possible patterned top constructionof FIG. 3. Such illustrates gate dielectric annulus 26 encircling withincontact opening 20. Electrically conductive gate layer 16 has beenpatterned to comprise a ring portion and an extension 27. Regardless,the bulk mass of layer 16 constitutes an annulus which encircles contactopening 20. The above described process provides but one example of amanner in which a gate dielectric layer is provided within contactopening 20.

Referring to FIG. 5, a layer 30 of semiconductive material is providedover second dielectric layer 18 and within contact opening 20 againstgate dielectric layer 26, and in electrical communication with diffusionregion 13. In this particular described embodiment, layer 30 is providedto completely fill the remaining open portion of contact opening 20.Semiconductive material layer 30 constitutes a layer from which achannel region and at least one of a source region or a drain region ofa thin film transistor are to be formed. The semiconductive material oflayer 30 within contact opening 20 defines an elongated and outwardlyextending channel region 31 the electrical conductance of which can bemodulated by means of the adjacent electrically conductive gate and gatedielectric layers 16 and 26, respectively.

Field effect transistor channel regions typically utilize some minimumconductivity doping, less than the doping concentrations of the sourceand drain, to provide desired conductance when modulated by the gate.Such can be provided in this example by in situ doping of layer 30during its deposition. Alternately, an ion implant can be conducted withsubsequent processing providing desired diffusion of the dopants.

The semiconductive material layer 30 is then conductively doped suchthat its portion lying outwardly of contact opening 20 forms one of asource or a drain region 32 of a thin film transistor. The dopingresults in an interface 34 being created relative to the outermostportions of layer 30 and that portion within channel region 31, suchthat portion 32 constitutes a highly doped electrically conductiveregion, while channel region 31 constitutes a semiconductive layercapable of being rendered conductive by applying suitable voltage togate layer 16. Note that advantageously in accordance with the preferredprocess, conductive doping of layer 36 is conducted using its thicknessto effectively prevent conductivity doping of channel region 31, withsuch doping being conducted without other masking of the channel regionby any separate masking layer. The effective thickness and dopingconditions for the outer portion of layer 30 effectively can be utilizedto prevent undesired conductivity enhancing doping of channel region 31.

In the above described embodiment; one of doped regions 32 of layer 30or diffusion region 13 of bulk substrate 12 constitutes a source regionof a thin film transistor, while the other of such constitutes a drainregion. Region 31 constitutes a channel region, with gate layer 16comprising an annulus which encircles thin film channel region 31. Bothof channel region 31 and diffusion region 32 are elongated, withdiffusion region 32 being oriented substantially perpendicular relativeto channel region 31 and also substantially parallel with bulk substrate14. Elongated channel region 31 and gate dielectric annulus 26 areperpendicularly oriented relative to bulk substrate 14.

If region 13 constitutes the drain region, then the thickness of oxidelayer 14′ defines the gate-drain offset dimension of the thin filmtransistor. As well known to those of skill in the art, a drain offsetis a region used in thin film transistors to reduce off current causedby thermionic field emission in the channel region near the drain. Ifregion 32 is the drain, then the thickness of layer 18 defines theoffset dimension. The thickness of gate polysilicon layer 16 defines thechannel length of the thin film transistor.

An alternate embodiment is shown and described with reference to FIG. 6.Like numerals from the first described embodiment are utilized whereappropriate, with differences being indicated by the suffix “a” or withdifferent numerals. In the depicted embodiment of wafer fragment 10 a,semiconductive material 30 a is provided to only partially fill theremaining portion of contact opening 20. Such forms an annulus 33 withincontact opening 20, with such annulus being utilized to comprise thechannel region of the resultant thin film transistor.

Layer 30 a can be doped in a single step to form diffusion regions 32 aand 35, one of which constitutes a drain region and the other of whichconstitutes a source region of the resultant thin film transistor.Accordingly, channel annulus 33 is elongated and oriented substantiallyperpendicularly relative to bulk substrate 12 and diffusion regions 32 aand 35. In this described embodiment, gate layer 16 comprises an annuluswhich surrounds thin film channel annulus 33. Again, the elongated andsubstantially vertical nature or orientation of channel region 33prevents conductivity doping from occurring therein when regions 32 aand 35 are doped by a highly directional perpendicular ion implantationdoping. In this embodiment, diffusion region 13 constitutes a node towhich electrical connection of a thin film transistor is to be made,while in the first embodiment example region 13 comprised an inherentpart of the thin film transistor. Diffusion region 13 might alternatelybe provided by out-diffusion of dopant material from region 35 fromsubsequent heating steps.

Desired minimum doping for the channel region of FIG. 6 can be providedby in situ doping or by ion implanting, such as angled implanting.

Yet another alternate preferred embodiment is described with referenceto FIGS. 7-11. Like numerals from the first described embodiment havebeen utilized where appropriate, with differences being indicated withthe suffix “b” or with different numerals. Referring first to FIG. 7,second electrically insulative dielectric layer 18 is provided with aninitial contact opening 50 therethrough to electrically conductive gatelayer 16. A preliminary electrically insulative layer 52 is providedover second dielectric layer 18 and to within initial contact opening50, with such layer less than completely filling contact opening 50.

Referring to FIG. 8, preliminary electrically insulative layer 52 isanisotropically etched to define an insulative annulus spacer 54 withininitial contact opening 50. Such facilitates or enables producing acontact opening inwardly of the spacers which is less than the minimumphotolithographic feature size which can be useable to produce thesmallest possible initial contact opening 50. For example, where aminimum available photolithographic width for contact opening 50 were0.32 micron, the resultant width of the opening after spacer etch can bereduced to 0.1 micron. As examples, if layer 18 is 1500 Angstroms thickand opening 50 is 3200 Angstroms in diameter, layer 52 is preferablyprovided to a thickness of from 500 Angstroms to 1200 Angstroms, with1000 Angstroms being most preferred. An anisotropic etch of a 1000Angstrom thick layer 52 will preferably be conducted as an over-etch of300 Angstroms, leaving layer 18 1200 Angstroms thick.

Referring to FIG. 9, a secondary contact 56 is etched throughelectrically conductive gate layer 16 and first dielectric layer 14.During such etching, insulative annulus spacer 54 and second dielectriclayer 18 are used as an etching mask. Diffusion regions 13 b is providedas shown.

Referring to FIG. 10, a secondary electrically insulative layer 58 isprovided over second dielectric layer 18 and insulative annulus spacer54 to within secondary contact opening 56, with such layer beingprovided to less than completely fill secondary contact opening 56.

Referring to FIG. 11, secondary electrically insulative layer 58 hasbeen anisotropically etched to define a gate dielectric layer annulus 26b within secondary contact opening 56. A subsequent semiconductive layer30 b is provided and doped as shown to provide diffusion region 32 b,and to provide channel region 31 b. An example thickness for layer 58 is200 Angstroms. Anisotropic etching of such a layer preferably includes a200 Angstrom over-etch, resulting in a final preferred thickness oflayer 18 of 1000 Angstroms.

The above described embodiments utilizing an annulus gate essentiallyenables provision of a channel region which is gated about all sides,thus enabling provision of smaller field effect transistors. Suchresults in a reduced consumption of substrate area, with such examplethin film transistors enabling the required area to be that of thecontact and the associated anisotropic spacer-like constructions.Conventional horizontal thin film transistors require additional areafor the channel, source and drain regions. Such also provides forimproved thin film transistor characteristics, due to gating of thechannel region on all sides which provides greater controllable on/offcurrents.

The above described method and embodiment further reduce overall maskcount in semiconductor processing. Since in the preferred embodiment thechannel region is substantially vertical, masks are not required toprotect the desired channel from the thin film transistor source anddrain implants. Depending on implementation, the channel region may evenbe completely sealed from the surface providing even greater protection,thus eliminating at least two masks.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1-35. (canceled)
 36. A wafer comprising: a transistor comprising: a substrate; a gate provided over the substrate and substantially surrounding an opening; a first source/drain region; a second source/drain region; semiconductive material proximate the gate and comprising a channel intermediate the first and second source/drain regions, wherein at least a portion of the channel is formed within the opening; and dielectric material formed intermediate the gate and the semiconductive material.
 37. The wafer of claim 36, wherein the semiconductive material partially fills the opening within the gate.
 38. The wafer of claim 36 further comprising an electrically insulative layer over the substrate and below the gate.
 39. The wafer of claim 36, wherein the transistor comprises a thin film transistor.
 40. The wafer of claim 36, wherein the dielectric material is formed within the opening, and wherein the dielectric material and the semiconductive material completely fill the opening within the gate.
 41. The wafer of claim 36, wherein at least a portion of the first source/drain region is formed above the opening of the gate.
 42. The wafer of claim 41, wherein at least a portion of the second source/drain region is formed below the opening of the gate.
 43. The wafer of claim 36, wherein the gate laterally surrounds dielectric material.
 44. The wafer of claim 36, wherein the dielectric material laterally surrounds the channel formed within the opening.
 45. The wafer of claim 36, wherein at least a portion of the first source/drain region is formed within the semiconductive material.
 46. The wafer of claim 36, wherein at least a portion of the first source/drain region is formed within the substrate.
 47. The wafer of claim 36, wherein the channel is formed elevationally above at least one of the first and second source/drain regions.
 48. The wafer of claim 36, wherein the channel comprises an elongated structure extending substantially perpendicularly to an upper surface of the substrate.
 49. A wafer comprising: a transistor comprising: a substrate; a gate provided over the substrate and substantially surrounding an opening, wherein the opening has a lateral cross-sectional dimension which is less than a minimum photolithographic feature size utilized for fabricating the transistor; a first source/drain region; a second source/drain region; and semiconductive material proximate the gate and comprising a channel intermediate the first and second source/drain regions.
 50. The wafer of claim 49, wherein the channel is formed within the opening.
 51. The wafer of claim 49, wherein at least a portion of the first source/drain region is formed above the opening of the gate.
 52. The wafer of claim 49, wherein the gate laterally surrounds the channel.
 53. The wafer of claim 49, wherein the transistor comprises a gate dielectric between the gate and the channel, and wherein the gate dielectric laterally surrounds the channel.
 54. The wafer of claim 49, wherein at least a portion of the first source/drain region is formed above the opening, and wherein at least a portion of the second source/drain region is formed below the opening.
 55. The wafer of claim 49, wherein the transistor comprises a thin film transistor.
 56. The wafer of claim 49 further comprising an electrically insulative layer over the substrate and below the gate.
 57. A semiconductor device comprising: a transistor comprising: a substrate; a gate provided over the substrate and substantially surrounding an opening; a first source/drain region comprising at least a portion formed partially below the opening; a second source/drain region comprising at least a portion formed partially above the opening; semiconductive material proximate the gate and comprising a channel intermediate the first and second source/drain regions; and a gate dielectric formed intermediate the gate and the semiconductive material.
 58. The semiconductor device of claim 57, wherein the channel is formed within the opening.
 59. The semiconductor device of claim 57, wherein the transistor comprises a thin film transistor.
 60. A semiconductor device comprising: a transistor comprising: a substrate; a gate provided over the substrate and substantially surrounding an opening, wherein the opening has a lateral cross-sectional dimension which is less than a minimum photolithographic feature size utilized for fabricating the transistor; first and second source/drain regions; semiconductive material proximate the gate and comprising a channel intermediate the first and second source/drain regions; and a gate dielectric formed intermediate the gate and the channel.
 61. The semiconductor device of claim 60, wherein the channel is formed within the opening.
 62. The semiconductor device of claim 60, wherein the transistor comprises a thin film transistor.
 63. A transistor comprising: a substrate; a gate provided over the substrate and substantially surrounding an opening; a first source/drain region comprising at least a portion formed partially below the opening; a second source/drain region comprising at least a portion formed partially above the opening; semiconductive material proximate the gate and comprising a channel intermediate the first and second source/drain regions; and a gate dielectric intermediate the gate and the channel.
 64. The transistor of claim 63, wherein the channel is formed in the opening and partially fills the opening.
 65. The transistor of claim 63 further comprising a thin film transistor.
 66. The transistor of claim 63, wherein the gate dielectric and the semiconductive material completely fill the opening within the gate.
 67. The transistor of claim 63, wherein the semiconductive material is provided within the opening and over the gate.
 68. The transistor of claim 63, wherein the opening is formed through an entirety of the gate.
 69. The transistor of claim 63, wherein at least a portion of the first source/drain region is formed within the semiconductive material.
 70. The transistor of claim 63, wherein at least a portion of the first source/drain region is formed within the substrate.
 71. A transistor comprising: a substrate; a gate provided over the substrate and substantially surrounding an opening over the substrate, the opening has a lateral cross-sectional dimension which is less than a minimum photolithographic feature size utilized for fabricating the transistor; first and second source/drain regions; and semiconductive material intermediate the first and second source/drain regions and comprising a channel.
 72. The transistor of claim 71, wherein at least a portion of at least one of the first and second source/drain regions is formed within the opening.
 73. The transistor of claim 71, wherein at least a portion of the semiconductive material is formed within the opening.
 74. The transistor of claim 71 further comprising insulative material provided intermediate the gate and the semiconductive material.
 75. The transistor of claim 71, wherein at least a portion of at least one of the first and second source/drain regions is formed above the opening of the gate.
 76. The transistor of claim 75, wherein at least a portion of at least one of the first and second source/drain regions is formed below the opening of the gate.
 77. The transistor of claim 71 further comprising a thin film transistor. 